Generally, in the fabrication of a complementary metal-oxide-semiconductor (CMOS) transistor, a selective area epitaxial (SAE) process is widely used to form source/drain regions. By using the selective area epitaxial process to provide stress, the channel mobility of the transistor is improved and the performance of the transistor is enhanced.
However, the efficacy of using the conventional selective area epitaxial process to increase the performance of the transistor is still unsatisfied.